Description
Date depot: 1 janvier 1900
Titre: Defect Tolerance in FPGA
Directrice de thèse:
Lirida NAVINER (LTCI (EDMH))
Domaine scientifique: Sciences et technologies de l'information et de la communication
Thématique CNRS : Non defini
Resumé:
This research project addresses the problem of designing defect tolerant FPGA. The design context is supposed to be fabless, so no action at physical/mask level is considered. The objective is to propose solutions to achieve this tolerance by implementing strategies that cover architectural and software aspects.
The thesis will focus on architecture issues. It means the research of mechanisms for analysis and improving tolerance to faults in BLE (basic logic element), CLE (configurable logic element), S (switch) and C (connection) blocks.
The obtained robust basic blocks will be used to construct the defect tolerant FPGA. Also, the improvements achieved at basic blocks level will be used to define the fault tolerance mechanisms required at the FPGA global architecture level.
Doctorant.e: Ben Dhia Arwa