Description
Date depot: 1 janvier 1900
Titre: Distributed real-time scheduling onto NoC architectures
Directrice de thèse:
Alix MUNIER (LIP6)
Directeur de thèse:
Dumitru POTOP-BUTUCARU (Inria-Paris (ED-130))
Domaine scientifique: Sciences et technologies de l'information et de la communication
Thématique CNRS : Non defini
Resumé:
Research context :
The AOSTE team of INRIA:
The AOSTE Team promotes the use of synchronous formalisms for the high-level modelling, the full formal design, and the distributed implementation satisfying real-time constraints of embedded software. The team builds upon prior work by its members on the SYNCCHARTS, ESTEREL, and SYNDEX formalisms, which included extensive algorithmic studies on dedicated modeling, compilation, analysis, and optimization techniques. Our main expertise is in the fields of formal semantics of synchronous reactive systems, and optimized mapping (i.e. distribution and scheduling) between application algorithms and physical architectures descriptions.
http://www.inria.fr/recherche/equipes/aoste.en.html
The ALSOC team of the “Embedded Systems-on-Chips” department of LIP6:
The “Embedded Systems-on-Chips” department of the LIP6 laboratory conducts research on the design of multiprocessor systems-on-chips (MPSoC), aiming at developing practical methods and tools for systems design. Within this department, the ALSOC team is conducting research on : hardware/software codesign (the DSX environment) , virtual prototyping (the SoCLib project), embedded real-time operating systems (project MUTEK), networks-on-chips (project SPIN), hardware/software communication models, formal verification methods, architecture of multi-core processors, and iterative compilation for embedded systems. Through ALSOC, the LIP6 laboratory is the initiator of the SoCLib national project for the development of an open modeling and simulation platform for MPSoCs.
http://www.lip6.fr/recherche/team.php?id=900
http://www.lip6.fr/recherche/team.php?id=920
PhD research work description :
Multi-processor systems-on-chip (MPSoCs) have recently emerged as a hardware architecture of choice in fields such as multimedia, telecommunications, and embedded control. Furthermore, when an MPSoC architecture is designed for flexibility and scalability, it often follows the network-on-chip (NoC) paradigm. In this paradigm, the processors, memories, and specialized IP blocks of the MPSoC are interconnected using point-to-point (P2P) lines and routers, much like in a telecommunication network. The P2P lines and the routers allow messages to be transferred from any source to any destination.
New methods are needed to allow the generation of correct and efficient code for such architectures, which are best modelled as distributed systems with particular interconnect mechanisms. In this thesis, we shall consider the problem of hard real-time scheduling of embedded control applications onto NoC-based MPSoCs. The main difficulties are the modelling of the communication subsystem and the definition of scheduling policies for the communications over the NoC. The thesis shall focus on regular interconnect topologies such as meshes, using the DSPIN NoC developed at LIP6 [4] as an experimentation platform. On the application side, we shall consider embedded control and streaming applications described in dataflow languages such as Scade, Simulink, Scicos, or Signal/Polychrony.
The first part of the thesis will determine which existing techniques for distributed real-time scheduling still work on NoC-based SoC architectures, and at which cost. Two main classes of approaches exist here:
-# Hard real-time scheduling techniques, which provide (worst-case) real-time guarantees. They usually consider very simple, high-level representations of the hardware architecture where, for instance, communications and synchronizations are instantaneous. Providing such a high-level representation of a complex communication system such as a NoC consists in defining communication and synchronization protocols and timing abstractions that induce large overheads in terms of time and network load (number of transmitted messages).
-# Fast simulation techniques, which efficiently exploit fine architecture details to speed up computation and communication, but little or no functional or timing predictability, and no real-time guarantees.
From the extensive review of existing approaches, we shall derive a low-level formal model for the hardware platform which is:
-* Closer to the actual hardware than existing models used in hard real-time approaches, so that determining elementary durations (by simulation or WCET analysis) provides results of good precision.
-* A high-enough abstraction level to support tractable analysis.
Typical aspects that need to be included in such a model include communication primitives (and their durations), particular routing or scheduling policies, etc. This platform description will allow us to evaluate the costs of the hardware abstraction (in terms of timing overhead) in the existing hard real-time scheduling approaches.
The second part of this thesis will consider the case where classical scheduling techniques are not applicable due to the synchronization overheads induced by the hardware abstractio
Doctorant.e: Djemal Manel