Description
Date depot: 1 janvier 1900
Titre: Energy efficient memory Architectures using advanced technology nodes
Directeur de thèse:
Amara AMARA (Non relevant)
Directeur de thèse:
Andrei VLADIMIRESCU (University of California, Berkeley)
Domaine scientifique: Sciences et technologies de l'information et de la communication
Thématique CNRS : Non defini
Resumé:
The overall objective of this study is to explore circuit concepts to optimize power consumption and performance of SRAM circuits implemented at advanced technology nodes. This optimization can be achieved at different levels of the SRAM hierarchy: cell, column, bank and memory-cut levels.
There are several existing techniques to achieve low-voltage operation and energy optimization. However, co-integration of these techniques without too much overhead at different levels of hierarchy is still missing. These techniques come with new challenges, especially when implemented using advanced technology nodes and for ultra low voltages. The main challenge at advanced technology nodes is the variation in the transistor parameters due to low feature size; while the main bottleneck at ultra-low voltage is performance degradation.
Another major concern is that a wide range of VDD operation is required for mobile multi-media applications to achieve energy efficiency. Although intelligent power-aware software exists, making the memory work for wide range-VDD is another challenge. Achievable yield is another challenge at advanced technology nodes (SIP and monolithic 3D integration with the given technology, should be explored for SRAM while taking energy efficiency into the consideration).
Our project aims to come up with a methodology to design the circuits addressing the above-mentioned challenges. It aims to fully utilize the merits of the technology (transistors) used for implementation. We plan to work with advanced FD-SOI 20nm process and other technology node design kits available from our current partners.
As the research community is making a transition towards Non-volatile memories, we expect this study will fulfill the existing requirements of the SRAM architecture and sensing circuitry in an efficient manner.
We expect this work to find widespread use for applications like biomedical electronics and mobile multimedia systems.
Doctorant.e: Shaik Khajaahmad