Description
Date depot: 1 janvier 1900
Titre: Memory and Real-Time Scheduling Analysis of EMBB Platforms Performed from High-Level Models
Directeur de thèse:
Renaud PACALET (LTCI (EDMH))
Directeur de thèse:
Ludovic APVRILLE (LTCI (EDMH))
Domaine scientifique: Sciences et technologies de l'information et de la communication
Thématique CNRS : Non defini
Resumé:
Baseband processing has become an important feature of today’s mobile platforms because the latter have to cope with a high number of air services (e.g., 3G, WIFI, GPS, . . . ). These services have in common several basic algorithms, therefore advocating for an architecture implementing these basic computations in a generic way, and thus being able to execute all air services in a flexible way. However, this flexible architecture should also be conceived with low power consumption and usability in mind.
A few years ago, the laboratory on Systems-on-Chip (LabSoC), an entity of Telecom ParisTech, has introduced - with other academic and industrial partners-, a hardware and software architecture for efficiently executing all air services taking into account flexibility, low cost, and low power consumption constraints. This architecture is based on a set of DSP units, each of them having one hardware accelerator, a microcontroller and an internal memory. The overall set of DSPs is controlled from a main processor, the internal memory of each DSPs being mapped in the one of the main processor. DMA transfers may be used between DSPs’ local memory and the global memory. Executing concurrent baseband applications within this architecture is non trivial because of the sharing of memory and computation resources between complex and timely constrained baseband processing. Currently, an efficient sharing of these resources must be manually programmed by an expert of the platform, thus limiting the usability of the platform. A solution would be to offer a simplify capture of those applications - including memory and computations need - , and to automatically derive a memory sharing scheme and computation resources schedule. Moreover, this automatic generation should guarantee that all applications respect their timing constraints (e.g., deadlines).
The LabSoC has defined a UML profile - called DIPLODOCUS [3] [1] - that implements the Y-methodology [2], with three main stages: (i) application modeling, (ii) architecture modeling and (iii) mapping. The DIPLODOCUS profile is implemented by an open-source toolkit named TTool [4]. The overall approach (DIPLODOCUS, TTool) is supported by several industrial companies (Texas Instruments, Freescale) and projects (e.g., EVITA). A Ph.D. thesis has already investigated the possibility to describe EMBB applications in DIPLODOCUS, and to automatically generate the control code for these applications. Unfortunately, this generated code does not take into account memory sharing nor computation scheduling: this is the main contribution that is expected in this Ph.D.
Doctorant.e: Enrici Andrea