Description
Date depot: 1 janvier 1900
Titre: Fault Tolerance Analysis of Digital Circuits and Systems
Directrice de thèse:
Lirida NAVINER (LTCI (EDMH))
Domaine scientifique: Sciences et technologies de l'information et de la communication
Thématique CNRS : Non defini
Resumé:
Modern generation digital ICs based on advanced technology node increasingly su er from process variability and are more susceptible to faults. This is due to their reduced dimensions, which negatively impact on system reliability. The most common approach for fault tolerance improvement consists of incorporating redundancy, either static or dynamic or hybrid of the both. Given that redundancy implies penalties (area, speed, power, etc), it is important to know how reliable a circuit is. Actually, this enables de ning how much redundancy is really necessary.
Several fault tolerance analysis solutions exist and they di er by the types of faults and of circuits which they can treat as well as by their implementation. Anyways a precise analysis is very expensive in terms of computing complexity. In this thesis, we will focus on the research of an e ective solution adapted to complex circuits (large number of gates, with combinatorial and sequential parts) subject to various types of faults and variations.
Doctorant.e: Wang You