Projet de recherche doctoral numero :4536

Description

Date depot: 1 janvier 1900
Titre: Certified and Optimizing Bit Slicing Compiler
Encadrant : Dagand PIERRE-EVARISTE (IRIF)
Directeur de thèse: Gilles MULLER (LIP6)
Domaine scientifique: Sciences et technologies de l'information et de la communication
Thématique CNRS : Non defini

Resumé: It is common knowledge that a modern computer manipulates 64-bit registers. Most programmers therefore have a deeply ingrained conception of the 'atom of computation' being a 64-bit value, which could represent a number or a pointer for example. Software bit slicing [Pornin'01], also called 'SIMD within a register' (SWAR) [Fischer'03], is a programming trick by which a 64-bit register is treated by the programmer as 64 1-bit registers. As a result, bitwise operations - for example, the logical negation of a 64-bit register - behave as a SIMD ('single instruction, multiple data') instruction on 64 1-bit registers: we can exploit bit-level parallelism and therefore increase the throughput of some algorithms. This technique is particularly exploited in cryptography for its improved throughput on some cryptographic primitives [Biham'97, Canright'05, Azad'07] but also for its resistance against timing-attack [Kasper'09].

Doctorant.e: Mercadier Darius