Projet de recherche doctoral numero :6269

Description

Date depot: 5 septembre 2019
Titre: Reliable and functionally safe Artificial Intelligence hardware
Directeur de thèse: Haralampos STRATIGOPOULOS (LIP6)
Domaine scientifique: Sciences et technologies de l'information et de la communication
Thématique CNRS : Non defini

Resumé: Typically artificial intelligence (AI) algorithms run in software on general-purpose central processing units (CPUs) or on giant servers in the cloud using clusters of CPUs. Due to concerns of latency, network bandwidth, and privacy, there now exists a trend to push AI from cloud to edge, where computation is largely or completely performed on distributed Internet-of-Things (IoT) devices. However, a CPU is too large to fit inside an IoT device and it needs far more power than a device battery can provide. Therefore, customized AI hardware, implemented with very large-scale integration (VLSI) circuits technology, is required that offers small form factor and energy efficiency. In addition, AI hardware is expected to serve as hardware accelerator allowing real-time learning and inference. AI hardware will play a crucial role in many applications, including IoT networks and autonomous vehicles. With the foreseen industrialization and high-volume production of AI hardware, designing reliable and functionally safe AI hardware is an emerging topic that is largely unexplored. AI hardware, as any other VLSI circuit, is subject to errors occurring during manufacturing, as well as to failures occurring in the field of operation due to ageing and wear-and-tear provoked by environmental stress. Even if only a small part of the AI hardware is faulty, this can have a serious deterioration in the learning capacity despite the existing modularity and high parallelism. In this thesis, we envision developing built-in self-test (BIST) methodologies that equip the AI hardware with the capability to identify and neutralize faulty synapses and neurons. This in turn will enable a faster and more robust learning, and will guarantee the demanded reliability and functional safety requirements. We envision developing versatile BIST circuitry that looks solely at the hardware independently of the cognitive task and data being processed. We will develop and validate by simulation BIST methodologies for three different artificial neural network (ANN) architectures, namely a convolutional neural network (CNN) architecture for deep learning, a spiking ANN architecture, and a RRAM-based ANN architecture using memristor crossbars. By the end of the thesis, we plan to design, fabricate, and demonstrate a hardware ANN with BIST capabilities.



Doctorant.e: Spyrou Theofilos