Description
Date depot: 13 juillet 2023
Titre: Neuromorphic Hardware Platform
Directeur de thèse:
Haralampos STRATIGOPOULOS (LIP6)
Domaine scientifique: Sciences et technologies de l'information et de la communication
Thématique CNRS : Intelligence artificielle
Resumé: Artificial Intelligence (AI) and Machine Learning (ML) algorithms have been a subject of interest for several decades now. Although AI and ML have gone through hype cycles of disappointment and enthusiasm, recent algorithmic advancements, in particular Deep Neural Networks (DNNs), as well as the availability of big data and the rapid growth of computing power, have renewed interest leading nowadays to applications in numerous distinct fields, i.e., robotics, medicine, autonomous vehicles, computer vision, speech recognition, natural language processing, gaming, etc.
DNN models are computationally intensive and from a hardware perspective this poses severe challenges of data storage, movement, and processing speed on conventional Central Processing Units (CPUs) with a traditional Von Neumann computer architecture. To this end, there are intense and on-going efforts nowadays towards designing dedicated and customized processors for AI, referred to as AI hardware accelerators, which belong to the larger family of domain-specific computing paradigms. Widely used AI hardware accelerators today are Graphics Processing Unit (GPUs) and Field-Programmable Gate Arrays (FPGAs), but orders of magnitude of energy-speed improvement can be achieved with Application-Specific Integrated Circuits (ASICs).
Another high incentive for designing AI hardware accelerators is to push the execution of AI algorithms from the cloud closer to the sources of data onto edge devices. This is driven by energy, bandwidth, speed, availability, and privacy requirements. More specifically, edge computing reduces the data transfer requirement thus saving energy and bandwidth. Saving bandwidth is important given the forecast that several tens of billions of edge devices will be connected to the internet in the near future. Several applications, e.g., autonomous vehicles, require low-latency real-time computation which is slowed down due to the communication with the cloud. Also, several applications require availability, thus they need to be less dependent on the communication with the cloud. Finally, handling data locally offers privacy as opposed to transmitting sensitive data over the cloud. Edge AI is a challenging objective since edge devices have limited resources and are often battery-operated. Typically, AI hardware accelerators embedded on edge devices perform only inference with the DNN model trained in software and uploaded upfront.
This PhD will focus on the design of a hardware accelerator for Spiking Neural Networks (SNNs) that form the basis of neuromorphic computing. SNNs mimic brain-like functionality and are considered to be the third generation of neural networks bridging the gap between ML and the biological brain in terms of speed and energy consumption.
Nowadays, there exists large-scale neuromorphic research platforms, such as Intel’s Loihi, IBM’s TrueNorth, and the SpiNNaker from the University of Manchester. These platforms allow mapping an arbitrary SNN on a fixed hardware layer but are still highly proprietary. For example, Intel upon request may grant access to use Loihi in the cloud for research purposes. On the other hand, in recent years they have been many neuromorphic chips and FPGA implementations demonstrated by academic groups.
This PhD will target an end-to-end architecture-to-Hardware Description Language (HDL) framework for SNN implementation. More specifically, the goal will be to develop a tool that allows users to automatically synthesize any arbitrary SNN in HDL (i.e., VHDL) starting from a high-level architectural description, i.e., number of layers, number of feature maps per layer, and neuron hyper-parameters. From a design perspective, the goal is a SNN hardware accelerator with small form factor and high energy efficiency, such that they it can be used in resource-constrained IoT nodes for near-sensor computation and near-sensor intelligence. Additional attributes will be on-line learning and fault-tolerance. The tool will provide a design ready to be flashed onto an FPGA for fast prototyping and experimentation. The design will be fully synthesizable so that the user can also proceed to an ASIC fabrication. Our group participates actively in the open hardware movement, so we are planning to make the framework open-source. The PhD may culminate in an ASIC fabrication using the open-source tool suite Coriolis for chip design.
Doctorant.e: Kling Paul